Low current SOT-MRAM for integration in functional devices Position filled

Host institution

ANTAIOS is a young technological start-up created in January 2017 to develop Spin Orbit Torque (SOT) MRAM technology. ANTAIOS is a pioneer of SOT-MRAM technology, finding its roots in the Spintec laboratory where SOT was discovered and where the core patents of SOT technology were filed. ANTAIOS’ business model is to develop the technology, and then to license its intellectual property to major industrial companies, such as IDM and foundries. Currently composed of 14 people, the company is expected to reach between, 15 to 20 people in 2021.

Antaios has expertise in both the development and testing of SOT-MRAM devices and in the design of SOT-MRAM memory arrays and full integrated circuits (ICs). The Antaios R&D team is mostly devoted to technology development but has strong links to the IC design team.


Marc Drouard (ANTAIOS) and Gilles Gaudin (UGA, CNRS) .


Thanks to its unique combination of sub-ns writing, potential infinite endurance, and non-volatility, SOT-MRAMs appear as the only credible candidate for fast memories replacement in the memory hierarchy (low level SRAM, latches). 

In a functional memory, millions of bit cells must be operated, and inevitable device to device parameter distribution must be characterized and considered for chip design. Indeed, those tiny variations will lead to performance limitations as well as to various failure modes limiting the reliability of the memory. 

To enable the design of reliable and high performance SOT-MRAM memories, it is mandatory to use a high-accuracy simulation model during the design phase. The accuracy and reliability of such model, and the capability to model multiple variations (device to device variations, stochastic behaviour…) are critical to enable proper interfacing of SOT-MRAM bitcell with CMOS control peripherals. Furthermore, the simulation must be fast enough and able to handle a large number of bits. Finally, this model must be fed with highest accuracy characterization data. 

Such a reliable simulation model, perfectly mimicking characterization data for millions of memory cells, does not exist for SOT technology whereas it is a must-have for the future of the SOT-MRAM industry. 

The overall objectives of this project are to: 

  • Demonstrate the first high-speed and low-power performance of SOT-MRAM memory arrays at the 40nm scale (MTJ diameter) on a statistically relevant number of devices (multiple Mb). 
  • Determine the specific failure modes related to SOT-MRAM bitcells. 
  • Develop and validate the first statistically representative simulation model to enable the design of the first high-performance SOT-MRAM memory macro. 
  • Develop innovative bitcell, circuit block and architecture to mitigate the performance limitation highlighted in the previous tasks (ECC, Redundancy…). 

To do this, the research project under the SPEAR project will involve: 

  • developing the appropriate characterization equipment (hardware/software). The PhD student will have access to all Antaios characterization systems and to the characterization systems of Antaios academic partners.  
  • statistically characterizing SOT-MRAM bitcells under various conditions. The experiments will include electrical characterization (RH loops, RI loops, BER, Aging, Retention Time, RC characterization, Voltage breakdown, Read-disturb…) under applied field and temperature and potentially some structural characterization (TEM). This will be done on patterned device wafers (blanket wafers, single cell arrays or complete SOT-MRAM memory chips).  
  • studying the main defect mechanisms and failure modes (electromigration, stochasticity, etc.) and highlighting their physical origin. 

Based on these findings, the student will develop a simulation model whose performance should mimic the statistically collected data. The time evolution of the magnetization resulting from the model will be compared to the real time evolution of the magnetization in actual devices collected by time-resolved electrical characterization during a 6-month secondment at ETHZ.  

In the remaining time, the student will propose, based on the developed model (such as SOT-MRAM based TCAM), innovative circuits mitigating the performance limitations (specific to the SOT-MRAM technology) highlighted earlier during the project. This will be done in close partnership with the IC design group. 


The successful candidate must

  • hold a master or engineering degree in physics or electronics;
  • have experience in instrumentation, electrical characterization, electrical circuit design and in software development is appreciated;
  • have strong knowledge in mathematics and statistics;
  • have good analytical skills, be thorough, organized and proactive;
  • be able to lead his project autonomously but must be a team player;
  • be able to communicate fluently in English. Knowledge of French would be valued but is not mandatory.

Planned Secondments

ETHZ (Zurich, Switzerland), under the supervision of Pietro Gambardella.
Due to the specificities of their IRPs, ESR13 and ESR14 will carry out a single 6-month secondment.

Registering University

UGA (Grenoble, France).

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