Design-Technology Co-optimization techniques for enablement of MRAM-based Machine Learning hardware Position filled

Host institution

Imec is a world-leading research and innovation hub in nanoelectronics and digital technologies. The machine learning program at Imec is leading the quest for computationally- and energy-efficient machine learning accelerators. Imec‘s machine learning research is driving the co-evolution of hardware and algorithms needed to facilitate the move to this new computational paradigm.


Dr. Arindam Mallik


Current research shows the limitations of devices to be used for Training Neural Networks due to limited precision. This PhD topic will focus to break the barrier of device engineering to enable true analog in memory computing for Machine Learning training algorithms. The approach adopted for such a device optimization would require optimization at every abstraction level of a computing system, starting from algorithm, architecture, circuits to device engineering. ML algorithms such as DNNs have realized important breakthroughs in a myriad of application domains. The core operations in DNN are MVMs and the dominant model today is to train DNN using software capabilities, which results in an extremely large consumption of energy. A DNN can be physically represented by crossbar arrays hardware with programmable resistors (referred to as weight memory devices). Ideally, DNN accelerators should consist of dense non-volatile memories, with large resistance (MOhm) and narrow parameters distribution. MRAM technology is a promising candidate for such an approach: their resistance can be arbitrarily tuned to reach values required for analogue MVMs. However, increasing MTJ resistance makes impossible the cell writing using STT. This is mitigated by making use of MRAM emerging writing concepts: SOT and VCMA. In addition, design solutions are proposed to create multi-level bit MTJs cells and are currently being prototyped for further demonstration. Within this context, this project will explore Design-Technology Co-optimization (DTCO) of MRAM-based ML hardware.

In this PhD, you will:

  • Explore Design-Technology Co-optimization (DTCO) of MRAM-based ML hardware, with a primary focus on SOT-MRAM and VCMA devices
  • Perform device-level characterization and optimization needed to enable a low-energy hardware solution,
  • Propose circuit design level to explore DTCO techniques for ML circuit implementation.

By performing this PhD at Imec, you will have the opportunities to contribute both to the fundamental understanding of the SOT physics as well as to enable the practical realization of SOT-MRAM using state-of-the-art industrial fabrication methods on 300mm wafers.

[1] S. Cosemans et al. IEDM (2019) [2] J. Doevenspeck et al. VLSI (2020)


  • Master’s in Computer Engineering, Electrical Engineering or Device physics
  • Fundamental knowledge in neural networks
  • Computer architecture, and circuit design skills
  • Owing to the international nature of the research center, good verbal and written communication skills in English is a must.

Although not mandatory for this position, following prior experience can be an asset:

  • Electrical device characterization
  • Knowledge within the field of magnetism, spintronics, magnetic tunnel junctions

Planned Secondments

ETH Zürich (Zurich, Switzerland), under the supervision of Pietro Gambardella.

NanOsc (Gothenburg, Sweden), under the supervision of Fredrik Magnusson.

Registering University

KU Leuven (Leuven, Belgium).

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